1. Field of the Invention
The present invention relates to a reference voltage generating circuit, and more particularly, to a reference voltage generating circuit employing active resistance devices to secure operational reliability of the circuit and to reduce a layout area thereof.
2. Description of the Related Arts
As semiconductor devices are fabricated with more precise manufacturing processes, the thickness of insulating layers (e.g., SiO2, Si3N4, etc.) in metal oxide semiconductor (MOS) devices becomes more thin. The thinner the layer, the more it is prone to dielectric breakdown caused by the power supply voltage. For more reliable operation, a fixed internal power voltage is needed independent of a variable external power voltage.
Reference voltage generating circuits generally employ semiconductor material layers, such as an intrinsic poly-silicon layer, an N+/P+ active layer, an N−/P− well layer, etc., as passive resistance devices. While resistance values of the resistance devices may be readily controlled using the intrinsic poly-silicon, it is an additional process to create an intrinsic poly-silicon layer.
The N+/P+ active layer used for a resistance device has disadvantages such that it is difficult to control a resistance value in the source/drain region of a MOS device, and it is also difficult to obtain a high resistance value due to heavy doping.
A resistance device using the N−/P− well layer may have a high resistance value. However, since the resistance value varies in a large range, it is difficult to control the resistance and to get a reliable resistance value and a layout area of the resistance device should be increased to get a suitable resistance value.
Conventional reference voltage generating circuits using passive resistance devices will be explained with reference to FIG. 1 and FIG. 2.
FIG. 1 illustrates a conventional threshold voltage type reference voltage generating circuit using a passive resistance device. In the reference voltage generating circuit, a resistor R and MOS transistors Q1, Q2, and Q3 are arranged to maintain a constant voltage near the threshold voltage of the MOS transistors and to obtain a temperature compensation effect. A resistor R1 is required to generate a reference voltage as shown in FIG. 1, and a high resistance should be used to minimize the current consumption of the circuit.
For example, if an external voltage EVcc is 5V, an internal reference voltage Vref is 2V, and the current consumption is limited to 1 μA, the resistance value of the resistor R1 is:R1=(5V−2V)/1 μA=3 MΩ.
In case that the resistor R1 is a passive resistance device such as an intrinsic poly-Si layer, an N+/P+ active layer, an N−/P− well layer, etc., the same problems as mentioned above occur in the reference voltage generating circuit in FIG. 1.
FIG. 2 illustrates a conventional current mirror type reference voltage generating circuit having a passive resistance device. The circuit includes PMOS transistors Q4 and Q5, NMOS transistors Q6 and Q7, and a resistor R.
In the reference voltage generating circuit in FIG. 2, the voltage between the gate and source of the NMOS transistor Q7 is designed to be equal to its threshold voltage Vt. In this case, assuming that the current flowing in the resistor R is 0.5 μA, the resistance value R becomes:R=Vt/0.5 μAand, for example, R=1.4 MΩ when Vt=0.7V.
However, in the reference voltage generating circuit in FIG. 2, if a passive resistance device such as an intrinsic poly-silicon layer, N+/P+ active layer, an N−/P− well layer, etc. is used for the resistance R, the reference voltage generating circuit has the same problems as mentioned above.
Although, compared with the reference voltage generating circuit in FIG. 1, the reference voltage generating circuit in FIG. 2 may be less affected by an external bias, the circuit in FIG. 2 needs a separate start-up circuit because its voltage characteristic may be degraded when its power voltage is turned on.
Examples of the reference voltage generating circuits employing passive resistance devices and current mirror circuits can be found in Korean Patent Laid Open 95-20658, Korean Patent Publication 95-10284, and Korean Patent Laid Open 96-35620. An example of the reference voltage generating circuit including a start up circuit is described in U.S. Pat. No. 5,565,811.